1. Field of the Invention
The present invention relates to the field of microelectronics.
The present invention more specifically relates to forming composite electronic chips that perform many functions of various types.
2. Discussion of the Related Art
An electronic system is formed of one or several electronic boards. Each board implements a set of functions, and for this purpose, it includes passive elements, hybrid circuits, and integrated circuits. An integrated circuit is formed of an electronic chip assembled on a support or in a package.
Integrating the functionalities of an electronic board in the same integrated circuit especially enables:
reducing the cost, since several thousands of chips are collectively formed on a same wafer;
increasing speed and reducing power consumption, since unwanted elements between the various functions are minimized within the same integrated circuit; and
increasing the reliability for all of these functions, since they are included in a single circuit.
However, all functionalities of an electronic board are not always simultaneously integrable in the same integrated circuit. Such is the case when the integration of one function block requires use of a first substrate type and the integration of another function block requires use of a second substrate type.
As an example, reference will be made to the case of a GSM portable phone. In such a phone, there is a radiofrequency portion, a block that processes intermediary frequencies, and an analog (baseband) signal processing. Other function blocks are also present. These blocks are, in particular, radio amplifiers, memories, and management and regulation of power supplies. Secondary elements such as a calculator may belong to the system.
Technological methods using a massive silicon substrate as in BICMOS processes (U.S. Pat. No. 5,953,600 which is incorporated herein by reference) enable integration on the same electronic chip of:
bipolar components operating at several gigahertz;
MOS transistors for complex digital and analog circuits;
active and passive components that form an electronic memory; and
power components.
However, these processes that use a bulk silicon substrate do not enable integration, with optimal electric characteristics, of passive components such as capacitors, resistors, and inductances.
The degradation of the characteristics of these passive components is caused by the presence of the substrate, which behaves like a ground plane having a high internal resistance. It creates capacitive and electromagnetic couplings over any component located close to it. In the case of radiofrequency applications, eddy currents are generated in the silicon substrate. These capacitive and electromagnetic couplings cannot be precisely calculated. Accordingly, a massive silicon substrate has a non-predictable effect on the passive components and, accordingly, on the integrated function blocks. For operating frequencies of several gigahertz, these effects may be redhibitory.
In the previously-mentioned example of a portable phone made with a BICMOS method, the specific cases of the resistance and of the inductance are now considered.
In a BICMOS process, resistors are used to bias the quiescent point of bipolar transistors. Such is the case, in particular, for the stages of radiofrequency signal amplification. The D.C. biasing current must be greater than a minimum value. The hazards of the used manufacturing process create an uncertainty about the value of the resistance to be obtained at the end of the manufacturing cycle. It is necessary to increase the average quiescent current to be sure to always be greater than the minimum quiescent current necessary to the proper circuit operation. Any uncertainty, due to the manufacturing process, concerning the value of the resistance to be obtained at the end of the process that causes a useless increase of the power consumption of the circuit. The operating autonomy of a portable phone is an essential feature. The manufacturing method must be able to form precision resistors.
These resistors also conduct an A.C. signal having a frequency of several gigahertz. The unwanted elements of the resistor, mainly the stray capacitance with respect to the substrate, must also be as small as possible.
The methods using a massive silicon substrate enable forming either single-crystal silicon resistors in the substrate or polysilicon resistors above a thick oxide layer. The value of a silicon resistor depends on the amount of active dopants and on the mobility of the carriers in the silicon layer. These two parameters are better controlled when the resistor is made of single-crystal silicon rather than polysilicon. For an industrial process, the reproducibility of resistors formed in single-crystal silicon is of 5%, while that of polysilicon resistors is 20%.
For a method using a massive silicon substrate, the single-crystal silicon resistors are formed in the silicon substrate and isolated therefrom by a junction. This junction has too high a junction capacitance for radiofrequency applications. It is then preferred, to the detriment of the power consumption of the system, to make the resistors in polysilicon despite the lack of reproducibility.
It would be desirable, for reducing the imprecision of the resistors, to use single-crystal silicon on insulator resistors. However, this is not practical with current methods of integrated circuit manufacturing on massive silicon.
The charge impedance of the transistors operating in radiofrequency ranges is often formed of an inductance. Since the frequencies are high, the value of this inductance is small, which makes it integrable. Practically, one or several spirals defined in a metal level are formed to obtain a value of the inductance of approximately 10 nH. The unwanted elements of this inductance then are:
the spiral resistance;
the different stray capacitances associated with the inductance, such as:
the capacitances between the spirals;
the coupling capacitances with the substrate;
the electromagnetic coupling with the substrate.
Either thick aluminum or copper, which have a low resistance, are used to form such inductances. These two metals, with the thicknesses used, are generally not available in the environment of current manufacturing methods. Further, copper is very contaminating for integrated active components. This makes the implementation of technological processes integrating these components expensive.
If the substrate is massive silicon, there exists a strong coupling between the electromagnetic field generated by the inductance and the conductive silicon of the substrate. The penetration depth of the electromagnetic field into the substrate ranges between 50 and 100 xcexcm for a substrate having a resistivity greater than 5 ohm.cm and for frequencies of a few gigahertz.
The electromagnetic coupling and the various unwanted elements mentioned hereabove degrade the quality factor of the inductance. This quality factor does not exceed 10 for inductances formed on a massive silicon substrate. It would increase to 40 for inductances formed above an insulator having a minimum thickness of 50 xcexcm by using a metal level of low resistance. This type of inductance cannot be formed in a manufacturing method using a bulk silicon substrate.
The integration of all components of a system, such as a portable phone, in a single integrated circuit requires compromises which result in an increase of power consumption and in performance losses. Some passive elements, in particular inductances, must be placed outside of the package containing the chip.
Another solution is the forming of a hybrid circuit including several chips, some at least of the chips being other than on bulk silicon to optimize the desired performances. In this case, it should be noted that:
the performances obtained with a hybrid circuit are a trade-off between those of the electronic board and those which could have been obtained with a single integrated circuit;
the cost is high since the hybridization is performed by handling each chip separately;
the performances are average, since the general bulk is high and there remain many unwanted elements; and
the reliability of the assembly depends on the mechanical quality of the components and on the quality of the various connections or weldings performed in the hybridization. This reliability is much lower than that of an integrated circuit.
An assembly of a plurality of chips is disclosed in the European patent application 0465227 but such an assembly raises problems to have the upper surfaces of the various chips exactly at the same level.
An object of the present invention is to provide a technique enabling implementation, within a same chip, of electronic functions requiring different substrates for their integration.
Another object of the present invention is to combine a method enabling forming passive components optimized for frequencies greater than several gigahertz with a technological process using bulk silicon.
A third object of the present invention is to provide a method enabling forming of electronic chips having the following features:
a lower cost then that obtained with hybrid techniques;
a reliability similar to that of a standard integrated circuit; and
maximum electric performances.
To achieve these and other objects, the present invention provides an electronic system integrated in a chip formed of a first elementary chip in which is set at least one second elementary chip so that the surfaces of the elementary chips are substantially in a same plane, said at least one second elementary chip being connected to the first elementary chip by at least one metal interconnection level.
According to an embodiment of the present invention, the electronic system is adapted to a portable phone and includes, in the second elementary chip, passive radiofrequency elements.
The present invention also provides an electronic chip formed of at least one second elementary chip set in a first elementary chip so that the surfaces of the elementary chips are substantially in a same plane, said at least one second elementary chip being connected to the first elementary chip by at least one metal interconnection level.
According to an embodiment of the present invention, the surfaces of the elementary chips forming the electronic chip exhibit level differences smaller than 10 micrometers.
According to an embodiment of the present invention, the second elementary chip is formed by using a sapphire substrate and the first elementary chip is formed by using a massive silicon substrate.
According to an embodiment of the present invention, the first elementary chip is formed in a heterogeneous substrate including a surface layer above a layer of different doping; and at least one cavity is dug into the entire thickness of the surface layer.
According to an embodiment of the present invention, the first elementary chip or said at least one second elementary chip includes at least one pad of dimensions at least equal to 10 xcexcm, used as a contact surface for the metal level interconnecting the first elementary chip to said at least one second elementary chip.
According to an embodiment of the present invention, one of the elementary chips includes a contaminating material connected to the metal interconnection level via a metal level formed before the contaminating material level.
The present invention also provides a method for setting a second elementary chip into a first elementary chip, including the steps of:
forming a first elementary chip on a wafer;
forming at least one cavity in the first elementary chip;
forming and cutting at least one second elementary chip having a height substantially equal to the depth of said cavity;
placing said at least one second elementary chip into said at least one cavity;
depositing an insulating layer; and
forming at least one metal interconnection level between the first elementary chip and said at least one second elementary chip.
According to an embodiment of the present invention, the substrate used to form the first elementary chip includes a first heavily-doped layer; the substrate used to form the first elementary chip includes a second layer of different doping; and the etch selectivity or an optical property between the second and the first layer is used to adjust the depth of the cavities dug into the substrate of the first elementary chip.
According to an embodiment of the present invention, first interconnection pads are formed on the first elementary chip; second interconnection pads are formed on said at least one second elementary chip; and a metal level defined by photolithography connects first and second interconnection pads.
According to an embodiment of the present invention, the interconnection pads of one of the elementary chips have dimensions greater than the possible lateral misalignment resulting from the setting of the second elementary chip into the first one.
According to an embodiment of the present invention, a second elementary chip is formed by using a silicon-on-sapphire technology and it includes inductances made in copper.
According to an embodiment of the present invention, a second elementary chip is formed by using a silicon-on-insulator technique and it includes resistors formed in single-crystal silicon.
According to an embodiment of the present invention, after creation of the cavities, a barrier layer is deposited on the wafer to cover the sides of the cavity.
According to an embodiment of the present invention, the first elementary chip is formed on a massive silicon substrate; and said at least one second elementary chip includes passive elements used in radiofrequency.
The foregoing objects, features, and advantages of the present invention, will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings.